/* CS 341 Spring 2002 */
/* Note segment 3 */
/* 24-Jan-2002 */
/* Taken by Apostolos Paul Pantazis */

Today: Focus on SPARC assembly language.

For those who are not up to speed: SPARC is the the CPU that will
be used for the Bulk of this class, a historicaly interesting design.

 --> Two types of Architectures were mentioned in class:
     1. CISC : Complex Instruction set computer.
     2. RISC : Reduced Instruction set computer.

     In (1) the idea is that a single machine instruction can do a lot
     of work. Prime example is the VAX.
     In (2) the idea is making the instructions simple but have the
     hardware execute them fast.

     * Look up David Patterson.

     SPARC : Scalable Processor Architecture.
             |--> 2-adress machine.
             |--> LOAD/STORE architecture.
             |--> SPARC has 32 registers
             |--> Pipeline design is implemented.

     * Whats is a Pipeline?
       Well, a Non-Pipeline machine is one were there exist a lot of clock
       cycles for one instruction and a particular instruction is
       completely finished executing before the next one is fetched. From
       this we could conclude that a Pipeline machine is one were a new
       instruction could be fetched while another instruction has still
       not finished executing (part of an instruction is done on one clock
       cycle and part of it on another).

       A little history os Complex Implementation Strategy computers:

       P5 Core --> Pentium I 80586
       P6 Core --> Pentium II + Pentium III
       Pentium IV --> out of order speculative execution, I am not sure
       whether I will need this instruction in the future but I will do
       part of it anyway.


           destination, source
       ADD     r3         r5    --> r3+=r5
       r0 --> always 0.

       1. aritmetic
       2. Logic
       3. Condition codes / branching
       4. Load/store
       5. word/size
       6. Register Windows **

       ** Register Windows: Were to provide with effect of stack
          plus spedd of registers. the idea is that we treat all
          registers as being the top of the stack and there exist
          special instructions for moving registers around.

      look up : Byte adressable + memory allignment.

      Schematics available upon request.